An FPGA typically includes a matrix of Configuration Latches, Configuration Control elements and matrix of Programmable Logic Blocks (PLB's), Routing Blocks and IO blocks. The functioning of each of the Programmable Logic Block is controlled by the Configuration Latches. Configuration Latches data is readback from FPGA to the FPGA controller for debugging the Field Programmable Gate Array. These Configuration Latches are responsible for the functionality implementation and routing between these programmable logic blocks and IO's.
FIG. 1 illustrates the conventional structure of an FPGA with the Configuration latch matrix, Vertical shift registers (VSR), Horizontal shift registers (HSR) and the Readback Register. The figure illustrates the conventional structure used for data readback from configuration latches. The data frames are fed from configuration latches, further data inputs from the Horizontal Shift Registers selects the configuration latches to be Readback and this readback data is used for debugging on the Logic Device.
FIG. 2 illustrates the circuit of a conventional Configuration Latch used. It has a select line connected to the NMOS transistor. When this select line is active high the data at input is applied to latch. Similarly the same signal can be used to readback data from the latch. The output of this latch is further used to control the function of FPGA.
As per the prior art described in U.S. Pat. No. 6,069,489, the Readback and Configuration of Latches is done sequentially. The data is outputted on a frame-by-frame basis, thereby increasing time consumed in the overall debugging cycle. The configuration latches are loaded by loading data into the VSR (Vertical shift register) and then enabling select line for transferring the data in VSR to column of configuration latches. This selection of configuration column of latches is done serially by HSR (Horizontal shift register). While configuring the latches the HSR serially enables the configuration lines. First the configuration data is loaded frame wise in the VSR (Vertical Shift Register) and then the select line of HSR is enabled which selects a column of configuration latches. After the select line enabled the data from VSR is transferred to column of configuration latches.
For readback, the HSR enables select line in serial fashion and the data from configuration latches is transferred to readback registers, from where the data is serially streamed out. Thus if readback of any specific frames required for testing an application, time would be consumed to stream all the frames sequentially, thereby lengthening the Readback time.
FIG. 3 shows the Horizontal Shift Register (HSR) used in prior art. The flip-flops are arranged as a serial shift register manner. During the configuration start operation the reset signal is generated. This reset signal sets the first Flip-flop, while reset all others. Thus enabling the first select line. As stated in prior art whenever the data has to be transferred from VSR to configuration latches the select line has to be enabled, which is provided by this HSR. When one frame of data from VSR is transferred then new data is loaded into VSR and clock is provided to HSR thus enabling next column of configuration latches.
HSR is also used for partial configuration. In partial configuration only few columns of configuration latches are required to be loaded. After resetting HSR the shifting of set bit is done, till desired column is reached. After which HSR is enabled thus enabling the corresponding columns of latches, which are loaded with the data in VSR.
The Problem in prior art is that the time consumed for readback data frames is substantial due to the sequential transfer of the data frames. Further, the complete shifting of the HSR is required for Readback.
A need is therefore felt for an improved digital circuit, to eliminate sequential implementation of Readback, for ultimately reducing the debugging time of an FPGA.